Modern electronic devices continue to shrink in size as they grow in capability. More and more tasks are being accomplished by fewer and fewer components.
The arena of analog and hybrid signal processing has special demands. Filters, voltage followers, and other analog and hybrid devices require analog functions that are not always easily accommodated in modern shrinking architecture. A limitation found in analog signal processing is the available die area and the power required for high speed operation. In even the best existing designs, filtering accuracy and gain come at the cost of decreasing speed and increasing complexity.
Prior fabrication techniques, too, have been unable to achieve some of the component combinations that help enable some analog and hybrid signal processing. The combination of n-channel and p-channel metal-oxide semiconductor (MOS) devices, especially transistors, has posed special challenges to fabrication.
One attribute associated with transistors is “threshold voltage,” generally defined as the input voltage at which the output logic level of the transistor changes state. Another definition of the term “threshold voltage” is the gate voltage above which the transistor becomes conductive in an enhancement mode field-effect transistor (FET) or nonconductive in a depletion mode FET. The operational speed of a transistor is a function of its threshold voltage. To increase speed, the threshold voltage is decreased. However, there is a tradeoff; with decreased threshold voltage, the drive current and leakage current of the transistors can be increased. Depending on the application of the transistor, a designer must select a particular threshold voltage for the transistor based on many factors, including speed and power consumption.
Types of transistors known in the art include those commonly referred to as NMOS (negative-channel metal-oxide semiconductor) devices and PMOS (positive-channel metal-oxide semiconductor) devices. The threshold voltage of these types of devices is dependent on the original doping concentration of the silicon substrate used as the foundation for forming the transistor.
For PMOS devices, the threshold voltage can be reduced by adjusting the original doping concentration using another, subsequent implantation of dopant into the substrate. In the case in which boron ions (or ions that include boron, such as BF2) are used as the dopant, this latter implantation is sometimes referred to as the “boron adjust.” More generally, it may be referred to as the “threshold adjust.” By adding dopant, particularly a p-type dopant that includes boron, the threshold voltage of a PMOS device is lowered.
As described above, NMOS devices having a particular threshold voltage can be fashioned by specifying the appropriate original doping concentration. However, according to the conventional art, a threshold adjust process for reducing the threshold voltage of such devices is lacking.
With the advent of techniques described in the above referenced application, low threshold NMOS and PMOS devices can be accommodated in a single chip. However, circuit design techniques required for hybrid and analog signal processing have not been developed to exploit low threshold NMOS and PMOS devices in the same chip.